• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention generates a PLL input reference frequency by frequency-adjusting an input 1.544 MHz reference signal frequency, and then varies the duty ratio to apply to an external PLL circuit, whereby a synchronized output clock of the external PLL circuit is synchronized. A PLL reference clock application device for preventing a phenomenon in which an instantaneous phase is distorted in a state, the apparatus comprising: a divider 100 for dividing an input reference signal frequency by 193; D-flip flops (210, 220) for outputting the frequency of 24KHz and 16KHz in synchronization with the input reference signal; A NAND gate 230 for performing an AND operation on each of the input frequencies and inverting the input frequencies; An AND gate 240 for ANDing each input frequency; A D-flip flop 250 for outputting the output frequency of the AND gate 240 in synchronization with an input reference signal; A D-flip flop 270 for synchronously outputting a frequency synchronously output by the D-flip flop 250 to an inverted reference signal frequency; And an AND gate 280 for multiplying the frequencies output from the D-flip-flops 250 and 270 to the external PLL circuit 300 as a reference signal. By adjusting the duty ratio of the PLL reference frequency generated by dividing the odd number to 50:50 and applying it to the high-precision external PLL circuit, the output main signal of the PLL circuit synchronized with the reference frequency is the desired high-precision stable frequency clock (10 -12). It is a very useful invention to be maintained at).
    公开号:KR19990081701A
    申请号:KR1019980015816
    申请日:1998-04-24
    公开日:1999-11-15
    发明作者:정영
    申请人:유태로；성미전자 주식회사；
    IPC主号:
    专利说明:

    PIEL standard clock application device
    The present invention relates to an apparatus for applying a PLL reference clock in a T1 / E1 converter, and more particularly, to generate a PLL input reference frequency by frequency-dividing and adjusting a 1.544 MHz reference signal frequency in an input T1 signal. Is applied to an external PLL circuit by variably adjusting the PLL reference clock application device so that the synchronized output clock of an external PLL circuit having a high precision (10 -12 ) clock frequency does not cause a momentary phase shift in a synchronized state. It is about.
    1 is a high precision as an exemplary network configuration of (10 - 12) receiving drive DE clock (clock drived) between the relay device provides a standard clock (Cesume- clock provided by atoms) of the relay device A is a high-precision (10 -12 ) receives the standard clock and transmits it to the B and C relays, and the B and C relays provided with the standard clock also receive the supplied standard clocks or held drive clocks with D and E. It has a structure of transmitting to the B, F, and G relays, respectively.
    In the above network configuration, if a clock is not input from the A relay device due to a bit transmission error or a line break on the L1 line, the B relay device has a lower precision input from the C relay device through the L2 line. It receives the clock of (<10 -10 ) and distributes it to the relays of D and E, respectively. In this case, the D relay receiving the divided clock has the precision of the clock input from the relay B (10 -9 ). Even if it is lower than the accuracy (<10 -10 ) of the clock that is auxiliary input to the D relay device can not be understood, there is a problem that the uncorrected clock provided by the B relay device is used unconditionally.
    In order to solve this problem, a new standard of a message (Bit Oriented Message (BOM) in T1 signal and SSM (Syncronus Status Message) in E1 signal) for indicating the accuracy of a clock transmitted between relays has been newly proposed. As a result, the D relay device that receives the new type of message indicating the accuracy of the received clock can grasp the accuracy of the clock that is currently being received from it, and can selectively receive and compare it with the accuracy of the clock that is auxiliary. It became.
    Accordingly, even in the T1 / E1 converter provided for signal conversion between the relay devices (B and D relay devices in Fig. 1) having different signal types, the accuracy of the converted message as well as the new type of message conversion described above is input. In order to ensure the reliability of the designation, when a high precision clock is input, the accuracy must be maintained and transmitted between the D relays. For this purpose, a high precision PLL circuit must be used.
    However, currently provided high-precision PLL circuits have a high-precision (<10 -12 ) oscillation clock, where the duty ratio of the PLL reference frequency applied thereto is not 50:50, i.e., the reference clock is converted into a T1 signal. In the case of using 1.544 MHz, the phase of the frequency clock outputted in synchronization from the PLL circuit may be momentarily distorted, resulting in a decrease in the accuracy of the clock provided by the T1 / E1 converter. Since the message is virtually independent of the accuracy of the clock being converted and transmitted at the time of T1 / E1 conversion, there is a problem of increasing the error rate in the relay operation of the latter relay apparatus using the clock information.
    Therefore, the present invention was created to solve the above problems, and by varying the duty ratio of the PLL reference frequency applied to the external PLL circuit, the synchronized frequency clock of the PLL circuit is a stable high precision frequency clock The purpose is to provide a PLL reference clock application device.
    1 is a high-precision exemplary network configuration of a drive clock de (drived clock) between the relay apparatus receives the standard clock (10 - 12) degrees,
    Figure 2 is a block diagram showing the configuration of an embodiment of a PLL reference clock applying apparatus according to the present invention,
    FIG. 3A shows the internal circuit of the divider of FIG.
    FIG. 3B shows an internal circuit of each counting element FTD in FIG. 3A,
    FIG. 4 shows a waveform diagram of the main part of the PLL reference clock application device of FIG.
    ※ Explanation of code for main part of drawing
    A, B, C, D, E, F, G ..,: Repeater 2: Multiplexer (MUX)
    3,210,220,250,270: D-Flip Flop
    11, 12, 13, 14, 15, 16, 17, 18: Counter element (FTD)
    100: divider 200: duty ratio variable circuit
    300: PLL circuit
    According to an aspect of the present invention, there is provided a PLL reference clock applying apparatus comprising: a dispensing means for dividing the reference clock by counting an input reference clock from an initial value that is repeatedly set; And adjusting means for varying the duty ratio of the divided frequency and applying it to an external PLL.
    The PLL reference clock application device according to the present invention configured as described above, first, the dispensing means counts an input reference clock clock starting from a value initially set, and sets the count value again when the count upper limit is reached. By repeating, a PLL reference signal of a predetermined frequency obtained by dividing the reference signal frequency by an odd multiple is generated and output. The adjusting means variably adjusts the duty ratio of the generated PLL reference frequency so that a PLL reference frequency having a duty ratio of 50% is applied to an external PLL circuit.
    Hereinafter, the configuration and operation of a preferred embodiment of the PLL reference clock applying apparatus according to the present invention will be described in detail with reference to the accompanying drawings.
    2 is a block diagram showing the configuration of an embodiment of a PLL reference clock application device according to the present invention, which divides a reference signal frequency of 1.544 MHz in an input T1 signal by 193; D-flip flops (210, 220) for outputting in synchronization with a reference signal of 1.544MHz input frequency of 24KHz and 16KHz of the internal frequency divided in the 193 frequency division process; A NAND gate 230 for performing an AND operation on the respective frequencies output from the D-flip flops 210 and 220 and inverting them; An AND gate 240 for ANDing the frequency of the 193-divided 8KHz and the inverted output frequency; A D-flip flop 250 for outputting the output frequency of the AND gate 240 in synchronization with an input 1.544 MHz reference signal; A D-flip flop 270 for synchronously outputting a frequency synchronously output by the D-flip flop 250 to an inverted reference signal frequency; And an AND gate 280 for multiplying the frequencies output from the D-flip flops 250 and 270 to the external PLL circuit 300 as a reference signal. The internal circuit of is capable of resetting to the respective values of the input terminals D0 to D7 as shown in Fig. 3A, and has a plurality of counting elements 11 to 18 having a toggle terminal; And a plurality of AND gates 20 to 28 for sequentially inputting the output value of the counting device at the front end to the toggle terminal at the top, each of the plurality of counting devices 11 to 18 as shown in FIG. 3B. XOR (1) for performing an exclusive OR on the current output value and the toggle signal; A multiplexer (2) for selecting one of the output value and the input data (D) of the XOR (1); And a D-flip-flop 3 which outputs the output value of the multiplexer 2 in synchronization with the input clock.
    First, the values of the input terminals D0 to D7 of the divider 100 are set to 63 (= 00111111 (2) ) as shown in the circuit diagram of FIG. 2 so as to divide the input reference signal frequency of 1.544 MHz into 193. The divider 100 counts a 1.544 MHz clock, which is a reference signal inputted from this value, and becomes 256. When the divider 100 reaches 256, the divider 100 receives the logic circuits 26, 27, and 28 in the divider 100. By reversing the selection signal value of the multiplexer 2, the initial setting value 63 is reset, and the counting process is performed again, thereby performing 193 division.
    During the dispensing process, each output terminal Q0 to Q7 of the divider 100 outputs a divided clock, and each frequency of the divider clock has Q0 of 772KHz, Q1 of 386KHz, ... Q4 is 64KHz, Q5 is 32KHz, Q6 is 16KHz and Q7 is 8KHz. However, since the divided value of the divider 100 is not a multiplier of 2, the divided clock does not have a duty ratio of 50%. For example, the final divided output signal Q7 is initially set when 65 is divided. Since the coefficient value becomes 128 by the value of 63, and the state changes, the duty ratio becomes 66.3% as shown in FIG.
    The circuit 200 at the rear end receiving the divided clock adjusts the duty ratio, and this operation is performed as follows.
    32 KHz and 16 KHz, which are output frequencies of the Q5 and Q6 stages, of the output frequency divisions are output to the D-flip flops 210 and 220, and 8 KHz, which is the final frequency division frequency of the Q7 stage, is input to the AND gate 240, respectively. Accordingly, the D-flip-flops 210 and 220 output the 32KHz and 16KHz frequencies to the NAND gate 230 in synchronization with a reference clock of 1.544MHz to be input, and the NAND gate 230. By multiplying the input clock signal of 16KHz and 32KHz and inverting the same, it outputs a signal as shown in ⓑ of FIG. 4 which becomes HIGH for 3/4 of the 128 clock period, and the AND gate 240 Is again logically multiplied by an input signal of 8 KHz (ⓐ in FIG. 4) and the inverted output frequency (ⓑ in FIG. 4), so that the signal state of FIG. 4 ⓐ is low in the inverted output signal of FIG. 4 ⓑ. Figure 4 ⓒ and the state change once by removing the section that becomes high when Output the same cycle clock.
    At this time, the signal output from the AND gate 240, the output signal of the two flip-flops (210, 220) input to the previous NAND gate 230 is delayed by one clock of the reference clock (1.544MHz) and output Therefore, the portion where both signals of the NAND gate 230 become high is delayed by one clock and is outputted. Therefore, its inversion section is 31 clocks less than 1/4 of 128 clocks, and conversely, the NAND gate 230 The high section of has a width of 97 clocks, so that the high output section of the AND gate 240 has a section width corresponding to 97 clocks.
    At this time, since the duty ratio of the signal output from the AND gate 240 is 97:96, which is not exactly 50%, in order to finely adjust this, adjust the circuit at the rear end by half a clock of the reference clock (1.544 MHz). do.
    To this end, the D-flip flop 250 outputs a frequency of 8 KHz input from the AND gate 240 in synchronization with a reference signal frequency of 1.544 MHz input, and the D-flip flop 270 at a rear end thereof. Is synchronized with the falling edge of the 1.544 MHz reference signal frequency inputted inverted by the inverter 260 at the clock input stage, i.e. The output is delayed by half a clock of the reference clock. As described above, the two signals output from the flip-flops 250 and 270 are input to the AND gate 280 which is the final output terminal in the form of ⓓ and ⓔ of FIG. 4, and the AND gate 280 is half clocked in phase. By multiplying the two signals of the wrong 8KHz frequency by input, the 8KHz signal is finely adjusted to 50:50 (96.5 frequency clocks of 1.544MHz each) as shown in Fig. 4, which is an external PLL. By applying as a reference frequency signal to the circuit 300, the frequency of 1.544 MHz generated from the high-precision external PLL circuit 300, the stable high-precision frequency clock (10 -12 ) does not cause instantaneous phase shift To be.
    The PLL reference clock applying device according to the present invention configured and operated as described above adjusts the duty ratio of the PLL reference frequency generated by dividing an input reference signal frequency to an odd number of 50: 50 and applies it to a high precision external PLL circuit. by, it would be very useful inventions to be held in a stable frequency reference frequency clock (10 - 12) with high accuracy to the desired output signal of the PLL circuit in synchronism with the.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] A dispensing means for counting the input reference clock from an initial value that is repeatedly set and dispensing the reference clock; And
    And adjustment means for varying the duty ratio of the divided frequency to apply to the external PLL.
    [2" claim-type="Currently amended] The method of claim 1,
    And a frequency of the input reference clock is 1.544 MHz, and the distributing means divides the reference clock into 193.
    [3" claim-type="Currently amended] The method according to claim 1 or 2,
    And fine adjusting means for finely adjusting the variable duty ratio by half a clock of the reference clock.
    [4" claim-type="Currently amended] The method of claim 3,
    And the duty ratio adjusted by the fine adjustment means is 50%.
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    同族专利:
    公开号 | 公开日
    KR100286695B1|2001-04-16|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-04-24|Application filed by 유태로, 성미전자 주식회사
    1998-04-24|Priority to KR1019980015816A
    1999-11-15|Publication of KR19990081701A
    2001-04-16|Application granted
    2001-04-16|Publication of KR100286695B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980015816A|KR100286695B1|1998-04-24|1998-04-24|Apparatus for applying pll reference clock|
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